I don’t have the Marvell datasheet handy, but recall seeing that when run a 1. With linux this indeed is a problem, when doing it correctly in devicetree then lots of errors come during boot, claiming PHY 0 is invalid, then PHY 0 is enabled, and working, and the second PHY with address 1 valid address remains not configured and is fully not accessible. Linux Kernel Thanks Panou. I have gotten a patch that looks like it applies to the It’s almost as if the default config of the PHY is enough to pass data to the eth1 interface even though it hasn’t been configured.
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Patch is applicable ONLY to the It’s likely that a hardware workaround in the fabric is easier to implement than digging into the Linux core software. Another question if I may, what about the dsa part ,arvell the tree, isn’t it required?
Linux source code: drivers/net/phy/marvell.c (v) – Bootlin
We have tried to apply the patch, but does’nt linx Again, this appears to be a software issue. I have looked at the following link, and it appears that 88e112 issue of supporting two PHYs was solved in I have tried that previously and once againt to verify.
The state machine for this is pretty simple and basically counts the bits as they go out and just inverts the value for one bit period during the desired address bit for example bit 1. Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.
Hoping to get a pre-release of the ilnux Add mdio in the top level: Thu Feb 18 Not sure about the dsa or link.
I cant try it due to my situation, if you try it can you please give information about I’ve tried your device tree example as well as different examples found: This seems to make sense, as all the other dual phy configurations I see have PHY addresses that aren’t zero. This has been tested on Zynq Ultrascale with a Daughter card. So I would suggest you to try testing the setup in We verified that before trying it in the kernel.
FYI, the patch is here, but not applicable to any of the current Xilinx kernel releases: I’m looking for some insight that I’m missing, or some other clue to indicate why the kernel drivers can’t detect PHY1 at address 1 correctly.
net: phy: marvell: fix Marvell 88E used in SGMII mode [Linux ] – Linux Kernels
Yes, I have tried it, but eth1 still doesn’t work. Did you try running ping with u-boot? Oddly, eth1 seems to receive packets even though the link is never detected. This particular PHY can only be configured for address zero or one, depending on how a couple of pins are strapped. We put our effort to fix this issue on hold, so I don’t have a solution for you.
Linux on P4080 + external PHY through RGMII: slow ping + total freeze without error message
Haven’t worked on this in a couple of years. I have gotten a patch that looks like it applies to the When we get back to the issue I will post whatever resolution we come up with.
I assume you use the same interface voltage for both PHY chips. I had seen that, but we run both PHYs a 1.
net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]
We have detected your current browser version is not the latest one. Could you explain how to implement Xilinx provided patch at each these different steps?
Linux Kernel Thanks Panou.
It will be fixed in the